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Evaluation data is gotten from a SRAM of 256 words times 4 bits ASIC.
The layout is made with a module generator. The SPICE netlist is
extracted by Dracula of Cadence.
- The circuit includes 10,451 MOS transistors, 43,433 resistors and
175,128 capacitors.
- The circuit is calculated by SUN Enterprise 450 with a main memory
of 2 Gbytes.
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