next up previous
Next: Accuracy Up: Evaluation of Embedded DRAM Previous: Reduction Rate

Simulation Time

Table 5 shows the lengths of simulation time by HSPICE before and after the reduction by THYME.

The original netlist required 21712.98 seconds while the reduced netlist required only 12663.96 seconds, reducing the simulation time to 58%.


Table: Comparison of simulation time.
netlist MOSFETs resistors capacitors time(sec)
original 6,387 2,156 9,231 21712.98
reduced 5,186 1,588 7,569 12663.96


If you have a question, please mail to:
Mathematical Systems Thyme reception <thyme-info@msi.co.jp>